The operating speeds and computing power of electronic systems continues to increase. As a result, the demand for semiconductor devices having higher speed and/or greater transfer rates has grown correspondingly. To meet such demands, many systems use synchronous dynamic random access memories (DRAMs) as opposed to asynchronous DRAMs. Synchronous DRAMs can provide faster access speeds and/or transfer rates than asynchronous DRAMs.
In pursuit of even higher access speeds and/or transfer rates, some semiconductor memories utilize "double-data rate" (DDR), as opposed to single data rate (SDR), approaches. A SDR semiconductor memory can perform data write operations in synchronism with a clock signal. That is, the fastest rate at which data can be written is one write per clock cycle. A DDR semiconductor memory can perform data write operations at twice the rate of an SDR device. That is, two writes can be performed to a DDR device per clock cycle. Some DDR devices can accomplish such faster write operations by writing data in synchronism with a first clock signal and a second clock signal, where the second clock signal is the inverse of the first.
Referring now to FIG. 5, a block diagram is shown illustrating a general purpose DDR-only data input circuit. The DDR-only data input circuit includes a first stage circuit 500 and five D-type flip-flop (FF) circuits 502 to 510. Write operations in the DDR-only data input circuit can be performed according three clock signals CLK, CLKB and DQS.
The input circuit of FIG. 5 can receive data at an input terminal DQ. Data received at the input terminal may be latched in various D-type flip-flops 502 to 510 according to the CLK, CLKB and DQS clock signals. Two data write operations can be performed in synchronism with each clock cycle.
DDR-type semiconductor devices normally operate in a DDR mode. Thus, the testing of a DDR-type semiconductor device can require three clock signals CLK, CLKB and DQS. In addition, a DDR-type semiconductor device can have stringent timing requirements, such as input signal set-up and hold times. It may not be possible for an ordinary memory tester to generate such multiple clock signals and/or meet more stringent timing requirements. Ordinary memory testers are typically designed to test SDR type memory devices.
Semiconductor devices may have input circuits that can be used in a DDR mode and an SDR mode. However such input circuits are typically very complex. Further, such circuits may result in the operation of circuits for one mode interfering with the operation of circuits in another mode.
In light of the prevalence of ordinary memory testers that are capable of testing in a SDR mode but are not sufficient for testing DDR modes, it would be desirable to arrive at some way of providing a semiconductor device having a DDR mode that may be tested with an ordinary (SDR mode) memory tester. Further, it would be desirable to provide such a semiconductor device without an overly complex circuit configuration.